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It has been quite a while since my last post about Lora gateway’s FPGA version. Finally we received the boards! The boards are manufactured by a Chinese PCB manufacture that I have been always using.
And it is really cheap! Compared to the IMST’s 189 EUR’s NON-FPGA version, our FPGA version(SX1301AP2-PCB_E336) has surpassed it totally!
Let’s see the performace:
Lowest record over the world for Lora: -143.3dBm
Amazing, uh? Much more better than IMST’s board(-134dBm)
First additional feature: spectral scan
The Background Spectral Scan (= RSSI histogram from SX1272) FSM consists to save the number of iterations that a RSSI value occurred.
To do so, there is a RAM inside the FPGA. The RAM address (over 8 bits i.e. 256 entries) corresponds to the read RSSI value from SX1272. Each time a RSSI value is read, the RAM data (16 bits) corresponding to the RAM_address (= RSSI value) is incremented by one.
You can find an example of how to run the Background Spectral Scan feature under our LoRa gateway
(GW) GitHub: https://github.com/lora-net/lora_gateway/tree/master/util_spectral_scan
The left one is CW=-20dBm, the right figure is CW=-110dBm
One more important feature that brings only by FPGA version: Listen-Before-Talk
We all know that ETSI has impose a regulation on the time on air, which is to limit the devices to occupy the spectrum for a long time.
But for the gateway if we comply 1%’s air time that would be a disaster since when 1000 nodes want to do Online-Activation or comfirmed data trasmission, the gateway will be dummy after sending several packets. Hence in this case we need LBT AFA to send the packets back to nodes.
Now this LBT AFA is released in the lora_gateway repo, server will be ready soon.